1 commercial temperature range idt74sstvf16859 13-bit to 26-bit registered buffer with sstl i/o august 2003 2003 integrated device technology, inc. dsc-6194/14 c idt74sstvf16859 commercial temperature range functional block diagram 13-bit to 26-bit registered buffer with sstl i/o description: the sstvf16859 is a 13-bit to 26-bit registered buffer designed for 2.3v-2.7v v dd for pc1600 - pc2700 and 2.5v-2.7v v dd for pc3200, and supports low standby operation. all data inputs and outputs are sstl_2 level compatible with jedec standard for sstl_2. reset is an lvcmos input since it must operate predictably during the power-up phase. reset , which can be operated independent of clk and clk , must be held in the low state during power-up in order to ensure predictable outputs (low state) before a stable clock has been applied. reset , when in the low state, will disable all input receivers, reset all registers, and force all outputs to a low state, before a stable clock has been applied. with inputs held low and a stable clock applied, outputs will remain low during the low-to-high transition of reset . applications: ? along with cspt857c, zero delay pll clock buffer, provides complete solution for ddr1 dimms features: ? 1:2 register buffer ? meets or exceeds jedec standard sstvf16859 ? 2.3v to 2.7v operation for pc1600, pc2100, and pc2700 ? 2.5v to 2.7v operation for pc3200 ? sstl_2 class i style data inputs/outputs ? differential clk input ? reset control compatible with lvcmos levels ? latch-up performance exceeds 100ma ? esd >2000v per mil-std-883, method 3015; >200v using machine model (c = 200pf, r = 0) ? available in 56 pin vfqfpn and 64 pin tssop packages the idt logo is a registered trademark of integrated device technology, inc. 51 48 49 45 35 r 1d c1 16 q 1a reset clk clk v ref d 1 to 12 other channels 32 q 1b
2 commercial temperature range idt74sstvf16859 13-bit to 26-bit registered buffer with sstl i/o pin configurations tssop top view function table (1) input reset clk clk d q outputs h ll h hh h l or h l or h x qo (2) lx x x l notes: 1. h = high voltage level l = low voltage level x = don?t care = low to high = high to low 2. qo = output level before the indicated steady-state conditions were established. absolute maximum ratings (1) symbol description max. unit v dd or v ddq supply voltage range ?0.5 to 3.6 v v i (2) input voltage range ?0.5 to v dd +0.5 v v o (3) output voltage range ?0.5 to v ddq +0.5 v i ik input clamp current, v i < 0 ?50 ma i ok output clamp current, 50 ma v o < 0 or v o > v ddq i o continuous output current, 50 ma v o = 0 to v ddq v dd continuous current through each 100 ma v dd , v ddq or gnd t stg storage temperature range ?65 to +150 c notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. the input and output negative voltage ratings may be exceeded if the ratings of the i/p and o/p clamp current are observed. 3. the output current will flow if the following conditions are observed: a) output in high state b) v o = v ddq vfqfpn top view q 1 2 a v d d q q 8 a q 1 1 a q 1 0 a q 9 a q 1 3 a g n d v d d q v d d q d 1 1 d 1 2 v d d d 1 3 5 6 4 3 q 6a q 7a q 5a q 4a q 3a q 2a q 1a q 13 b v dd q q 12b q 11b q 10b q 9b q 8b 1 14 d 4 d 5 d 6 d 7 reset d 8 d 9 d 10 gnd clk clk v ddq v dd v ref 42 29 v d d q d 1 q 6 b q 7 b v d d q q 5 b q 4 b q 3 b q 2 b q 1 b d 2 v d d v d d q d 3 1 5 2 8 gnd q 13a d 1 q 12a d 2 gnd gnd v ddq v ddq d 3 d 4 d 5 d 6 d 7 q 6a q 7a v ddq q 8a reset d 8 d 9 d 10 d 11 d 12 v dd gnd d 13 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 q 11a q 10a q 9a q 5a q 4a q 3a q 2a q 1a gnd q 13b v ddq q 12b q 11b q 10b q 9b q 6b q 7b q 8b gnd v ddq q 5b q 4b q 3b q 2b q 1b gnd gnd clk clk v ddq v dd v ref gnd gnd v ddq v dd gnd v ddq
3 commercial temperature range idt74sstvf16859 13-bit to 26-bit registered buffer with sstl i/o pin description pin names description q 1 - q 13 data output gnd ground v ddq output-stage drain power voltage v dd logic power voltage reset asynchronous reset input - resets registers and disables data and clock differential input recievers v ref input reference voltage clk positive master clock input clk negative master clock input d 1 - d 13 data input - clocked in on the crossing of the rising edge of clk and the falling edge of clk center pad ground (mlf package only) symbol parameter test conditions min. typ. max. unit v ik control inputs v dd = 2.3v, i i = ? 18ma ? ? ?1.2 v v oh v dd = 2.3v to 2.7v, i oh = -100 av dd ? 0.2 ? ? v v dd = 2.3v, i oh = -8ma 1.95 ? ? v ol v dd = 2.3v to 2.7v, i ol = 100 a ? ? 0.2 v v dd = 2.3v, i ol = 8ma ? ? 0.35 i i all inputs v dd = 2.7v,vi = v dd or gnd ? ? 5 a i dd static standby i o = 0, v dd = 2.7v, reset = gnd ? ? 0.01 ma static operating i o = 0, v dd = 2.7v, reset = v dd , v i = v ih (ac) or v il (ac) ??20 dynamic operating (clock only) i o = 0, v dd = 2.7v, reset = v dd , v i = v ih (ac) or v il (ac) ,? 6? a/clock clk and clk switching 50% duty cycle. mhz i ddd dynamic operating i o = 0, v dd = 2.7v, reset = v dd , v i = v ih (ac) or v il (ac) ,?43? a/clock (per each data input) (1) clk and clk switching 50% duty cycle. one data input mhz/data switching at half clock frequency, 50% duty cycle. input data inputs v dd = 2.5v, v i = v ref 310mv 2 ? 3 c i clk and clk v icr = 1.25v, v i (pp) = 360mv 2 ? 3 pf reset v i = v dd or gnd 2 ? 3 note: 1. power dissipation levels will allow operation at ddr333 speeds without excessive die temperature. dc electrical characteristics over operating range for pc1600 - pc2700 following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, v dd = 2.5v 0.2v, v ddq = 2.5v 0.2v
4 commercial temperature range idt74sstvf16859 13-bit to 26-bit registered buffer with sstl i/o symbol parameter test conditions min. typ. max. unit v ik control inputs v dd = 2.5v, i i = ? 18ma ? ? ?1.2 v v oh v dd = 2.5v to 2.7v, i oh = -100 av dd ? 0.2 ? ? v v dd = 2.5v, i oh = -8ma 1.95 ? ? v ol v dd = 2.5v to 2.7v, i ol = 100 a ? ? 0.2 v v dd = 2.5v, i ol = 8ma ? ? 0.35 i i all inputs v dd = 2.7v,vi = v dd or gnd ? ? 5 a i dd static standby i o = 0, v dd = 2.7v, reset = gnd ? ? 0.01 ma static operating i o = 0, v dd = 2.7v, reset = v dd , v i = v ih (ac) or v il (ac) ??20 dynamic operating (clock only) i o = 0, v dd = 2.7v, reset = v dd , v i = v ih (ac) or v il (ac) ,? 6? a/clock clk and clk switching 50% duty cycle. mhz i ddd dynamic operating i o = 0, v dd = 2.7v, reset = v dd , v i = v ih (ac) or v il (ac) ,?43? a/clock (per each data input) (1) clk and clk switching 50% duty cycle. one data input mhz/data switching at half clock frequency, 50% duty cycle. input data inputs v dd = 2.6v, v i = v ref 310mv 2 ? 3 c i clk and clk v icr = 1.3v, v i (pp) = 360mv 2 ? 3 pf reset v i = v dd or gnd 2 ? 3 note: 1. power dissipation levels will allow operation at ddr400 speeds without excessive die temperature. dc electrical characteristics over operating range for pc3200 following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, v dd = 2.6v 0.1v, v ddq = 2.6v 0.1v operating characteristics, t a = 25oc (1) symbol parameter min. typ. (1) max. unit v dd supply voltage v ddq ? 2.7 v v ddq output supply voltage pc1600-pc2700 2.3 2.5 2.7 v pc3200 2.5 2.6 2.7 v ref reference voltage (v ref = v ddq /2) pc1600-pc2700 1.15 1.25 1.35 v pc3200 1.25 1.3 1.35 v tt termination voltage v ref ? 40mv v ref v ref + 40mv v v i input voltage 0 ? v dd v v ih ac high-level input voltage data inputs v ref + 310mv ? ? v v il ac low-level input voltage data inputs ? ? v ref ? 310mv v v ih dc high-level input voltage data inputs v ref + 150mv ? ? v v il dc low-level input voltage data inputs ? ? v ref ? 150mv v v ih high-level input voltage reset 1.7 ? ? v v il low-level input voltage reset ? ? 0.7 v v icr common-mode input range clk, clk 0.97 ? 1.53 v v i (pp) peak-to-peak input voltage clk, clk 360 ? ? mv i oh high-level output current ? ? ? 16 ma i ol low-level output current ? ? 16 t a operating free-air temperature 0 ? +70 c note: 1. the reset input of the device must be held at v dd or gnd to ensure proper device operation.
5 commercial temperature range idt74sstvf16859 13-bit to 26-bit registered buffer with sstl i/o timing requirements over recommended operating free-air temperature range pc1600 - pc2700 pc3200 symbol parameter min. max. min. max. unit clock clock frequency ? 200 ? 220 mhz tw pulse duration, clk, clk high or low 2.5 ? 2.5 ? ns t act differential inputs active time (1) ?22?22ns t inact differential inputs inactive time (2) ?22?22ns t su setup time, fast slew rate (3, 5) data before clk , clk 0.65 ? 0.65 ? ns setup time, slow slew rate (4, 5) 0.75 ? 0.75 ? ns t h hold time, fast slew rate (3,5) data before clk , clk 0.75 ? 0.65 ? ns hold time, slow slew rate (2,5) 0.9 ? 0.8 ? ns switching characteristics over recommended free-air operating range (unless otherwise noted) pc1600 - pc2700 pc3200 symbol parameter min. max. min. max. unit f max 200 ? 220 ? m h z t pdm clk and clk to q 1.1 2.6 1.1 2.4 ns t pdmss clk and clk to q (simultaneous switching) ? 2.9 ? 2.68 ns t phl reset to q ? 5 ? 5 ns notes: 1. data inputs must be low a minimum time of t act max., after reset is taken high. 2. data and clock inputs must be held at valid levels (not floating) a minimum time of t inact max., after reset is taken low. 3. for data signal input slew rate is 1v/ns. 4. for data signal input slew rate is 0.5v/ns and <1v/ns. 5. clk, clk signal input slew rates are 1v/ns.
6 commercial temperature range idt74sstvf16859 13-bit to 26-bit registered buffer with sstl i/o test circuits and waveforms for pc1600 - pc2700, v dd = 2.5v 0.2v for pc3200, v dd = 2.6v 0.1v voltage waveforms - pulse duration notes: 1. c l includes probe and jig capacitance. 2. i dd tested with clock and data inputs held at v dd or gnd, and i o = 0ma. 3. all input pulses are supplied by generators having the following characteristics: prr 10mhz, z o = 50 , input slew rate = 1 v/ns 20% (unless otherwise specified). 4. the outputs are measured one at a time with one transition per measurement. 5. v tt = v ref = v ddq /2 6. v ih = v ref + 310mv (ac voltage levels) for differential inputs. v ih = v dd for lvcmos input. 7. v il = v ref - 310mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos input. 8. t pdm is t pd with one output switching. t pdmss is t pd with all outputs switching. load circuit voltage waveforms - setup and hold times voltage waveforms - propagation delay times voltage waveforms - propagation delay times voltage and current waveforms inputs active and inactive times timing input v icr v i(pp) t plh t phl output v oh v ol v icr v tt v tt v oh v ol v ih v il t phl v dd /2 v tt lvcmos reset input output v ref v ih v il v ref input t w v ref v ih v il v ref input v icr v i(pp) t su t h timing input from output under test test point lvcmos reset input v dd /2 v dd t inact t act i dd v dd /2 90% 0v (see note 2) 10% v tt c l =30pf (see note 1) r l =50
7 commercial temperature range idt74sstvf16859 13-bit to 26-bit registered buffer with sstl i/o ordering information idt74sstvf xxx xx package device type pa pag nl nlg thin shrink small outline package tssop - green thermally enhanced plastic very fine pitch quad flat no lead package vfqfpn - green 13-bit to 26-bit registered buffer with sstl i/o 0c to +70c (commercial) 859 16 xx family double-density xx process blank corporate headquarters for sales: san jose, ca 95138 fax: 408-284-2775 www.idt.com
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